coreboot-4.19-784-g787d0bd6d1-dirty Fri Mar 10 05:06:26 UTC 2023 x86_32 bootblock starting (log level: 7)...
FMAP: area COREBOOT found @ 670200 (1637888 bytes)
CBFS: mcache @0xfeff0e00 built for 13 files, used 0x2dc of 0x4000 bytes
CBFS: Found 'fallback/romstage' @0x80 size 0x16158 in mcache @0xfeff0e2c
BS: bootblock times (exec / console): total (unknown) / 33851 ms


coreboot-4.19-784-g787d0bd6d1-dirty Fri Mar 10 05:06:26 UTC 2023 x86_32 romstage starting (log level: 7)...
full_reset() called!


coreboot-4.19-784-g787d0bd6d1-dirty Fri Mar 10 05:06:26 UTC 2023 x86_32 bootblock starting (log level: 7)...
FMAP: area COREBOOT found @ 670200 (1637888 bytes)
CBFS: mcache @0xfeff0e00 built for 13 files, used 0x2dc of 0x4000 bytes
CBFS: Found 'fallback/romstage' @0x80 size 0x16158 in mcache @0xfeff0e2c
BS: bootblock times (exec / console): total (unknown) / 33850 ms


coreboot-4.19-784-g787d0bd6d1-dirty Fri Mar 10 05:06:26 UTC 2023 x86_32 romstage starting (log level: 7)...
SMBus controller enabled
Setting up static northbridge registers... done
Initializing Graphics...
Back from systemagent_early_init()
Intel ME early init
Intel ME firmware is ready
ME: Requested 8MB UMA
Starting native Platform init
DMI: Running at X4 @ 5000MT/s
FMAP: area RW_MRC_CACHE found @ 620000 (65536 bytes)
MRC: no data in 'RW_MRC_CACHE'
ECC supported: no ECC forced: no
ECC RAM unsupported.
SPD probe channel0, slot0
  Row    addr bits  : 15
  Column addr bits  : 10
  Number of ranks   : 2
  DIMM Capacity     : 4096 MB
  CAS latencies     : 5 6 7 8 9 10 11
  tCKmin            :   1.250 ns
  tAAmin            :  13.125 ns
  tWRmin            :  15.000 ns
  tRCDmin           :  13.125 ns
  tRRDmin           :   6.000 ns
  tRPmin            :  13.125 ns
  tRASmin           :  35.000 ns
  tRCmin            :  48.125 ns
  tRFCmin           : 160.000 ns
  tWTRmin           :   7.500 ns
  tRTPmin           :   7.500 ns
  tFAWmin           :  30.000 ns
channel[0] rankmap = 0x3
SPD probe channel0, slot1
SPD probe channel1, slot0
SPD probe channel1, slot1
ECC is disabled
Starting Sandy Bridge RAM training (full initialization).
100MHz reference clock support: no
PLL_REF100_CFG value: 0x0
Trying CAS 11, tCK 320.
Found compatible clock, CAS pair.
Selected DRAM frequency: 800 MHz
Selected CAS latency   : 11T
MPLL busy... done in 10 us
MPLL frequency is set at : 800 MHz
Selected CWL latency   : 8T
Selected tRCD          : 11T
Selected tRP           : 11T
Selected tRAS          : 28T
Selected tWR           : 12T
Selected tFAW          : 24T
Selected tRRD          : 5T
Selected tRTP          : 6T
Selected tWTR          : 6T
Selected tRFC          : 128T
Done dimm mapping
Update PCI-E configuration space:
PCI(0, 0, 0)[a0] = 0
PCI(0, 0, 0)[a4] = 1
PCI(0, 0, 0)[bc] = 82a00000
PCI(0, 0, 0)[a8] = 7ce00000
PCI(0, 0, 0)[ac] = 1
PCI(0, 0, 0)[b8] = 80000000
PCI(0, 0, 0)[b0] = 80a00000
PCI(0, 0, 0)[b4] = 80800000
PCI(0, 0, 0)[7c] = 7f
PCI(0, 0, 0)[70] = ff800000
PCI(0, 0, 0)[74] = 0
PCI(0, 0, 0)[78] = ff800c00
Done memory map
Done io registers
Done jedec reset
Done MRS commands
Logic delay 2 greater than 1: 0 0
Logic delay 2 greater than 1: 0 1
Aggressive read training failed: 0, 0, 1
RAM training failed, trying fallback.
ECC supported: no ECC forced: no
SPD probe channel0, slot0
  Row    addr bits  : 15
  Column addr bits  : 10
  Number of ranks   : 2
  DIMM Capacity     : 4096 MB
  CAS latencies     : 5 6 7 8 9 10 11
  tCKmin            :   1.250 ns
  tAAmin            :  13.125 ns
  tWRmin            :  15.000 ns
  tRCDmin           :  13.125 ns
  tRRDmin           :   6.000 ns
  tRPmin            :  13.125 ns
  tRASmin           :  35.000 ns
  tRCmin            :  48.125 ns
  tRFCmin           : 160.000 ns
  tWTRmin           :   7.500 ns
  tRTPmin           :   7.500 ns
  tFAWmin           :  30.000 ns
channel[0] rankmap = 0x3
SPD probe channel0, slot1
SPD probe channel1, slot0
SPD probe channel1, slot1
ECC is disabled
Starting Sandy Bridge RAM training (full initialization).